1. Field of the Invention
The present invention relates to latch and register circuits, and more particularly to a fast dynamic register.
2. Description of the Related Art
Dynamic logic circuits often exhibit relatively long setup and/or hold times to ensure proper operation. In many dynamic register circuits, the data had to be held while the clock was at a particular state, which was significantly disadvantageous for certain clock signals at or near 50% duty cycle. In a fast path of a digital circuit, buffers were often required to hold the data for the requisite amount of time. Buffers, however, consume valuable space and power. One method of reducing the hold time was to provide a pulsed clock generator. A pulse clock generator, however, also consumes valuable space and power.
There is a need for providing a fast dynamic register circuit with minimal setup and hold times without the overhead of buffers and/or pulsed clock circuits.